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CC80TSV-0101JY




Chip Structure

  • Base Layer : P-TEOS*
  • Metal Layer : TiN / AI-0.5%Cu
  • Passivation Layer : HDP* / P-SiN

*TEOS : Tetraethoxysilane
*HDP : High Density Plasma

 

 

Specifications CC80TSV-1 CC80TSV-2
Wafer Size 8 inch 8 inch
Wafer Thickness 100μm 100μm
Chip Size 7.3mm ♦ 7.3mm ♦
Pad pitch 80μm staggered (Peripheral)
300μm Full area (Center core)
80μm staggered (Peripheral)
300μm Full area (Center core)
TOP Side
Electrode Electroless Ni/Au plating
Bump Size Φ48μm (Option: φ42um)
Bump Height 8 ~ 12um
Electrode Cu + SnAg
Bump Size 38μm ♦ (Option: φ42um)
Bump Height Cu20μm + SnAg15μm
BOTTOM Side
Electrode Electroless Ni/Au plating
Bump Size Φ48μm (Option: φ42um)
Bump Height 8 ~ 12um
Electrode Electroless Ni/Au plating
Bump Size Φ48μm (Option: φ42um)
Bump Height 8 ~ 12um
Scribe width 120μm 120μm
    ♦ Bottom Side





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